CSE402 / COA
Syllabus
References:
[⤓] CSE402-REFERENCE-COMP-ORG-ARCH
Resources
M1: Overview of COA
[⤓] CSE402-M1-FACULTY-RESOURCE
MODULE 1 - CSE402 - STRUCTURED-SYLLABUS
Introduction to Computer Organization and Architecture
Basic organization of a computer
Block-level description of functional units
Performance Measures
Performance metrics of computer architecture
Bus and I/O Connectivity
Introduction to buses
Bus structure
Connecting I/O devices to CPU and memory
M2: CPU & Register Transfer Operations
[⤓] CSE402-M2-FACULTY-RESOURCE-Part-1
[⤓] CSE402-M2-FACULTY-RESOURCE-Part-2
MODULE 2- CSE402 - STRUCTURED-SYLLABUS
Instruction and Register Fundamentals
Instruction codes
Computer registers
Computer instructions
Register Transfer Language (RTL)
Timing and Control
Timing mechanisms
Control mechanisms
Instruction cycle
Memory and I/O Operations
Memory reference instructions
Input-output and interrupt reference instructions
Arithmetic Operations
Signed multiplication
Booth’s algorithm
Division of integers
Restoring division
Non-restoring division
Floating-point arithmetic
Addition
Subtraction
M3: Processor Org & Architecture
MODULE 3 - CSE402 - STRUCTURED-SYLLABUS
CPU Architecture
Introduction to CPU architecture
General register organization
Stack organization
Instruction Representation
Instruction formats
Instruction types
Control Unit Design
Hardwired control unit
Micro-programmed (soft-wired) control unit
Microinstruction sequencing and execution
Micro operations
Design of control unit
Control memory
Address sequencing
Data and Program Handling
Addressing modes
Data transfer and manipulation
Program control
Instruction Set Architectures
Reduced Instruction Set Computer (RISC)
Complex Instruction Set Computer (CISC)
Accumulator Logic
Design of accumulator logic
M4: Memory Organisation
MODULE 4 - CSE402 - STRUCTURED-SYLLABUS
Memory Fundamentals
Memory hierarchy
Memory characteristics
Cache Memory
Concept of cache memory
Cache architecture (L1, L2, L3)
Mapping techniques
Cache coherency
Other Memory Types
Interleaved memory
Associative memory
Virtual Memory
Concept of virtual memory
Segmentation
Paging
Page replacement policies
M5: I/O Org. & Peripherals
MODULE 5 - CSE402 - STRUCTURED-SYLLABUS
Input/Output Systems
I/O modules
I/O processor
Data Transfer Techniques
Programmed I/O
Interrupt-driven I/O
Direct Memory Access (DMA)
Pipeline and Parallel Processing
Pipeline processing
Arithmetic pipeline
Instruction pipeline
RISC pipeline
Parallel processing
Introduction to parallel processing systems
Notes
MidTerm
[⤓] CSE402-COA-M1-MidTerm-Concept-Outline
[⤓] CSE402-COA-M2-MidTerm-Concept-Outline
EndSem
[⤓] CSE402-PYQ+PROBABLE-QS+STRUCTURED-OUTLINE-COA
Question Directory
[⤓] CSE402-COA-Practise-Qs-Paper-Faculty
Assignment Questions
Previous Year Questions
[⤓] Y2S4-CSE402-COA-MidTerm-PYQ-APR25
[⤓] Y2S4-CSE402-COA-EndTerm-PYQ-Jun22
[⤓] Y2S4-CSE402-COA-EndTerm-PYQ-Jun23
[⤓] Y2S4-CSE402-COA-EndTerm-PYQ-Jun24
[⤓] Y2S4-CSE402-COA-EndTerm-PYQ-Jun25
External Sources
Last updated
